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dsPIC30F
FIGURE 9-3:
QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
TQCKPS<1:0>
Sleep Input
TQCS
2
Synchronize
Det
T CY
0
1
Prescaler
1, 8, 64, 256
1
QEIM<2:0>
0
TQGATE
D
CK
Q
Q
QEIIF
Event
Flag
16-bit Up/Down Counter
QEA
Programmable
Digital Filter
Quadrature
2
(POSCNT)
Reset
Encoder
UPDN_SRC
Interface Logic
Comparator/
0
QEICON<11>
3
Zero Detect
Equal
QEIM<2:0>
QEB
INDX
1
Programmable
Digital Filter
Programmable
Digital Filter
3
PCDOUT
Existing Pin Logic
Mode Select
Max Count Register
(MAXCNT)
UPDN
1
Up/Down
? 2005 Microchip Technology Inc.
DS70043F-page 29
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